The invention relates to methods and apparatus for controlling the delivery of power to a load, and more particularly relates to power control techniques that improve reliability and reduce power consumption.
Information technology (IT) equipment rooms (also known as data centers) utilize hundreds or even thousands of units of IT equipment. Each piece of IT equipment receives primary power by plugging into an outlet of a power distribution unit (“PDU”). A PDU is also a piece of IT equipment and typically includes: (a) a high power inlet from which power is received (typically from a panel board); (b) multiple lower power outlets; and (c) (optional) circuit breakers or fuses to protect the outlets from over current conditions (short circuits, etc.). PDUs are often designed to report certain status information over a communication and/or input/output interface, including: (a) the voltage being supplied to a given PDU's inlet, (b) how much power is flowing in the inlet and each outlet, and (c) the trip state (whether voltage is present) of each circuit breaker.
Additionally, each PDU may include the capability of turning the output voltage on and off in response to microcontroller signaling. This capability permits some level of software control over the power being delivered from each output of the PDU to much, if not most, of the of the IT equipment. The capability of turning the output voltage on and off may also provide a means of preventing rather significant in-rush currents to flow when main power is lost and then recovered. Indeed, when main power is first provided to a PDU (after having been lost of intentionally turned off), it is desirable to ensure that the output voltage to most if not all of the IT equipment connected to that PDU is off. If the output voltage were not initially off, then a very large in-rush of current to the IT equipment would occur, possibly tripping one or more circuit breakers protecting the PDU. However, assuming that the output voltage to individual pieces of IT equipment (or reasonably sized groups thereof) may be individually turned on in sequence, the aggregate current supplied by the PDU to the all IT equipment may be controlled and gradually ramped up.
FIG. 1A illustrates a block diagram of a conventional system 10 for controlling a single output of a PDU. The system 10 includes a microcontroller 12, an electromechanical relay 14, and a driver circuit 16. The microcontroller 12 is capable of producing a signal on a general-purpose-input-output (GPIO) pin that controls the state of the output voltage (e.g., 120V AC) delivered to the output of the PDU, labeled AC LOAD. The AC LOAD represents whatever IT equipment (not shown) is connected to the PDU. For brevity and clarity, this description will not go into extensive detail as to the hardware, firmware, and/or software functionality of the microcontroller 12. Suffice it to say that there are numerous conditions under which it is desirable for the microcontroller 12 to turn ON, turn OFF, and FLOAT the signal on the GPIO pin. It is noted that while there may be tens, hundreds, or thousands of GPIO pins in the system 10, the description here is concerned with one such pin, which description may be extended to other GPIO pins in the system 10.
In general, the state of the GPIO pin provides a control signal to the driver circuit 16, which in turn controls the state of the relay 14, thereby either connecting or disconnecting the output voltage (e.g., 120 VAC) to the AC LOAD.
The electromechanical relay 14 includes a coil and at least one set of contacts. It is assumed that the relay 14 is “normally open,” which means that when the coil is not energized (no current, iC, is flowing through the coil), the contacts assume an OFF (open) state and the current path between the set of contacts is open. In the OFF state, there is no current path from the 120V AC node to the AC LOAD. When the coil is energized, where current, iC, is flowing through the coil, a magnetic field produced by the coil causes the contacts to pull in and assume an ON state, where the current path between the set of contacts is closed. In the ON state, there is a current path from the 120V AC node to the AC LOAD, thereby energizing the load.
If a standard relay 14 is employed, then the driver 16 would have to provide the current iC to the coil of the relay 14 in order to keep the normally-open contacts closed. The level of power utilized to maintain the normal relay 14 in the ON state is typically 0.4 watts. In a data center containing 2000 PDUs, where each PDU contains 24 relays, the power consumption to maintain the relays in the ON state would be 19,200 watts. Although normally closed relays are available, there are fail safe problems with their use and they too would consume excessive power in order to keep them OFF for any long period of time. This is very undesirable.
There are, however, ways to reduce the total power consumed for maintaining relays in the ON and/or OFF state, which result in a direct financial benefit for the data center operator and a competitive advantage for the PDU manufacturer. In particular, one may employ a so-called latching relay 14 in the system 10 instead of a normal relay. The latching relay 14 only uses power briefly to latch the contact state to ON or OFF. Once latched ON or OFF, no further power is required to maintain the commanded state. A detailed discussion of the system 10 employing a latching relay 14 is given below.
With further reference to FIG. 1B, the GPIO pin exhibits a tri-state output, where the state of the GPIO pin may be OFF (e.g., 0 volts), ON (e.g., 1 volt), or FLOAT (e.g., a high impedance). When the GPIO pin is OFF, the potential is at a logic low (e.g., 0 volts) and the pin is capable of sinking current (into a relatively low impedance). When the GPIO pin is ON, the potential is at a logic high (e.g., 1 volt) and the pin is capable of sourcing current (from a relatively low impedance). When the GPIO pin is at the FLOAT state, the pin operates as a relatively high impedance input, and assumes a potential dictated by the circuitry external to the microcontroller 12.
The driver 16 controls the current iC through the coil of the relay 14 in response to the potential on the GPIO pin. In the illustrated example, between time=0 and t1, it is assumed that the GPIO pin is in the FLOAT state, there is no current through the coil of the relay 14, the contacts of the relay are open, and there is no voltage delivered to the AC LOAD. Between time t1 and t2, the command to provide voltage to the AC LOAD is given and the GPIO pin provides an ON potential of about 1 volt to the driver circuit 16, which in turn produces a positive pulse of current iC (X=33 mA) to the coil of the relay 14. The pulse of current iC through the coil causes the contacts to be pulled in and latched ON, thereby providing output voltage to the AC LOAD, even after time t2 (when the pulse is gone). Between time t3 and t4, the command to remove voltage to the AC LOAD is given and the GPIO pin provides an OFF potential of about 0 volts, pulsed of otherwise, to the driver circuit 16, which in turn sinks a pulse of current iC (−X=−33 mA) from the coil of the relay 14. The negative pulse of current iC through the coil causes the contacts to be latched OFF, thereby providing no output voltage to the AC LOAD (see potential A), even after time t4 (when the pulse is gone).
The above latching relay implementation of the system 10 overcomes the excessive power consumption problem discussed above. In addition, under certain conditions, the system 10 may be used to address the problem of in-rush current because the timing of turning ON the individual relays may be controlled by the microcontroller 12. However, under other conditions, the system 10 may not address the problem of in-rush current. Indeed, referring again to FIG. 1B, the system 10 may deliver output voltage to all the loads of the PDU by sequentially turning on the relays 14, by pulsing the respective coils, such pulse for a single such coil being shown from time t5 to t6. Thereafter, at time t7, main power may be lost. The loss of power, however, does not result in any of the relays 14 being turned OFF because they are latching relays, which would remain in the latched ON state. Meanwhile, power to all of the IT equipment would reduce to zero and such equipment would sit idle until power is again applied. At time t8, the main power may be restored, which would result in the output voltage (see potential B) being immediately and simultaneously applied to all of the AC LOADs, and a large in-rush current through all of the relays 14 to the AC LOADs, which is clearly an undesirable result.
Thus, although the prior art systems address some inherent disadvantages of the conventional PDU systems, the known solutions are unsatisfactory in the context of both the aforementioned undesirable power dissipation inefficiencies and in-rush current conditions. There are, therefore, needs in the art for new methods and apparatus for controlling the power delivery to the load, which address the efficiency issue and the in-rush current issue.